DocumentCode :
2723096
Title :
Testability preserving transformations in multi-level logic synthesis
Author :
Rajski, Janusz ; Vasudevamurthy, Jagadeesh
Author_Institution :
VLSI Design Lab., McGill Univ., Montreal, Que., Canada
fYear :
1990
fDate :
10-14 Sep 1990
Firstpage :
265
Lastpage :
273
Abstract :
The authors present a very efficient new method for the decomposition and factorization of Boolean expressions, which produces irredundant multilevel networks. The method is based on very simple objects, namely, double-cube divisors and single-cube divisors with only two laterals. It is demonstrated that these objects, despite their simplicity, provide a very good framework for reasoning about common algebraic divisors and duality relations between expressions. Since both the time and space complexity of the operations on double-cube and single-cube divisors is polynomial in the size of the two-level representation, the algorithms run much faster than those based on kernels. It is shown both theoretically and experimentally that the decomposition and factorization transformations introduced preserve testability, which implies that a complete test set developed for an input network also gives complete coverage of faults in the synthesized multi-level network
Keywords :
Boolean algebra; logic CAD; logic testing; polynomials; Boolean expressions; algebraic divisors; combinatorial logic; decomposition; double-cube divisors; factorization; irredundant multilevel networks; multi-level logic synthesis; polynomial; reasoning; single-cube divisors; testability; transformations; two-level representation; Automatic logic units; Circuit faults; Circuit synthesis; Circuit testing; Design optimization; Laboratories; Logic circuits; Logic design; Logic functions; Logic testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Conference, 1990. Proceedings., International
Conference_Location :
Washington, DC
Print_ISBN :
0-8186-9064-X
Type :
conf
DOI :
10.1109/TEST.1990.114032
Filename :
114032
Link To Document :
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