Sequential logic synthesis for testability using register-transfer level descriptions

A synthesis-for-testability approach that uses a register-transfer level (RTL) specification of a sequential circuit to derive a fully testable implementation of the circuit is presented. Emphasis is placed on the development of a synthesis strategy of don t care exploitation and logic partitioning that results in a fully testable implementation of the sequential machine. Preliminary experimental results indicate that large sequential circuits (e.g., finite-state-machine controllers, data paths) with a large number of latches and gates can be synthesized to be fully nonscan testable by use of these techniques