Novel secret-key IPR protection in FPGA environment

Some VLSI IP owners prefer to leave programming their IP into a field programmable gate array (FPGA) to the end customer. A major concern is the possible over-deployment of the IP into more devices than originally licensed. In this paper, the authors proposed a system based on secured handshaking with encrypted device and design authentication information ensuring that the IP can only be deployed into agreed upon devices. The system consists of hardware-supported design encryption and secured authentication protocols.