Electrical analyses of TSV-RDL-bump of interposers for high-speed 3D IC integration

As the progress of the packaging technology for the electronic consuming devices, the customer demands more and more. From the trend of the development on electronic devices, it shows that these demands require for more functions or higher density of devices within a limited space. By the capabilities of the 3D-IC technology, it could support such a design with multi-purposes including a smaller size, the high-speed and multi-functions. There are many approaches and technologies to make the 3D-IC. Amount of them, the stacking with Through-Silicon-Via (TSV), plays a very important role. It shortens the path of the circuit in a device. And hence, this device may support a faster operation. In this study, we analyze the different designs based on two TSV technologies, the Cu-filled and coaxial-type TSVs. By using the simulation approach, we evaluate the performances of these proposed designs. And, the results in our study should have the benefits for designing the interposer substrates which are used for developing the 3D-IC.