FPGA implementation of the "pyramids" block cipher

Author

Alkalbany, Abdullah ; Al Hassan, Hussien Ahmad ; Saeb, Magdy

Author_Institution

Dept. of Comput., Arab Acad. for Sci., Alexandria

fYear

2005

fDate

19-23 Sept. 2005

Firstpage

271

Lastpage

275

Abstract

The "PYRAMIDS" block cipher is a symmetric encryption algorithm of a 64, 128, 256-bit length, that accepts a variable key length of 128, 192, 256 bits. The algorithm is an iterated cipher consisting of repeated applications of a simple round transformation with different operations and different sequence in each round. The algorithm was previously software implemented in C++ code. In this paper, a hardware implementation of the algorithm, using field programmable gate arrays (FPGA), is presented. In this work, the authors discussed the algorithm, the implemented micro-architecture, and the simulation and implementation results. Moreover, a detailed comparison with other implemented standard algorithms was presented. In addition, the floor plan as well as the circuit diagrams of the various micro-architecture modules was presented

Keywords

cryptography; field programmable gate arrays; logic design; 128 bit; 192 bit; 256 bit; 64 bit; C++ code; FPGA implementation; PYRAMIDS block cipher; data communication security; field programmable gate arrays; iterated cipher; symmetric encryption algorithm; Application software; Counting circuits; Cryptography; Data security; Field programmable gate arrays; Floors; Hardware; Mathematics; Scheduling algorithm; Software algorithms; FPGA; VHDL; algorithm; cryptography; data communication security; encryption; micro-architecture;

fLanguage

English

Publisher

ieee

Conference_Titel

SOC Conference, 2005. Proceedings. IEEE International

Conference_Location

Herndon, VA

Print_ISBN

0-7803-9264-7

Type

conf

DOI

10.1109/SOCC.2005.1554509

Filename

1554509