Scan test architectures for digital board testers

The authors consider the problems posed by boundary scan sequences which are long and which contain meaningful vector data, constant data, and irrelevant or don´t care bits arbitrarily interspersed. They use the model of meaningful data within a frame of constant or irrelevant bits as a means of handling vector data efficiently, and they propose the sequencing and control features of the general-purpose digital tester as an efficient way to implement these frames. The simple architecture, that adds a serial data memory to a tester with flexible vector sequencing capabilities can handle many complex scan applications easily and efficiently. Additional types of data generators, such as pseudorandom generators and memory address generators, allow even more types of circuits to be tested by the scan paths method, although self-test methods give much smaller run times. By means of a specific example, it is shown that the performance achieved and the data storage resources required compare favorably with approaches based on special-purpose framing hardware