Design and implementation of a shared buffer architecture for a gigabit Ethernet packet switch

In this paper, the authors explored the design issues of shared buffer architecture capable of buffering fixed and variable sized packets for a 10G Ethernet switch. The design and implementation of a shared buffer circuit based on Xilinx Virtex 4 FPGA technology was presented. The proposed architecture is economic from the resource sharing point of view and is capable of supporting buffer bandwidths in excess of 31 Gbps using standard FPGA technology.