A high-speed pin-memory architecture using multiport dynamic RAMs

The authors describe a novel pin-memory design based on multiport dynamic video RAMs (VRAMs). Each pin (or channel) has a 512 K pattern depth allows a 100-MHz vector rate, and is economical in both size (3×1.5 in) and cost (less than $100). These achievements were made possible by a VRAM-oriented pin-memory architecture and the associated memory control circuitry, which are instrumental in facilitating the following features: the arbitration of the read/write and refresh operations, the coordination of two processors that access the memory at different stages of a test cycle, the provision for as many pins as possible to share components to reduce the overall cost and space, and the preservation of the independence of an individual pin so that it can be either active or idle for a particular burst regardless of the status of the others. The design described has been fully implemented in the High Speed Test System (HSTS) and functions successfully