A novel multiplier for high-speed applications

This paper describes a design of 8-bit times 8-bit unsigned multiplier. High-throughput rate is achieved by a new architecture implementing the earlier multiplication technique (Khatibzadeh et. al, 2005) in conventional register pipelining at the bit level. The multiplier is designed in 0.18-mum CMOS process. HSPICE simulation results indicate that the multiplier operating rates up to 6 GHz under the supply voltage of 1.8V. The empirical results show that our multiplier consumes only 63% (approx.) of the power of Baugh-Wooley multiplier with 40% reduction in latency