Title :
Arrangement of latches in scan-path design to improve delay fault coverage
Author :
Mao, Weiwei ; Ciletti, Micheal D.
Author_Institution :
Dept. of Electr. & Comput. Eng., Colorado Univ., CO, USA
Abstract :
A problem involving the arrangement of latches in a scan-path design to improve the coverage of delay faults is described. The problem is NP-hard, and a heuristic algorithm is introduced for solving this arrangement problem. A necessary and sufficient condition is also given to determine whether there is a scan path to implement a given delay-fault test pair. Only LAM (latch-arrangement-mapping) implementable test pairs need to be simulated by a delay-fault simulator for a semi-completed LSSD (level-sensitive-scan-design) circuit. Preliminary experimental results show that the proposed algorithm can find a LAM with better fault coverage than a randomly selected ones
Keywords :
fault location; logic design; logic testing; delay fault coverage; delay-fault simulator; heuristic algorithm; latch-arrangement-mapping; level-sensitive-scan-design; scan-path design; Circuit faults; Circuit testing; Delay; Design methodology; Heuristic algorithms; Latches; Logic testing; Sequential analysis; Springs; Sufficient conditions;
Conference_Titel :
Test Conference, 1990. Proceedings., International
Conference_Location :
Washington, DC
Print_ISBN :
0-8186-9064-X
DOI :
10.1109/TEST.1990.114046
