Testing for parametric faults in static CMOS circuits

The authors compare the cost of testing for excess of I _DDQ caused by bridge, break, and transistor stuck-on faults versus the cost of traditional testing methods. It is shown that, since many defects, cause nonlogical faults, I_DDQ monitoring during the application of test vectors to an IC provides significantly higher defect coverage than using only conventional testing. The costs for I_DDQ testing are compared with those for SSF (single-stuck-at-fault) testing by modifying an existing SSF ATPG (automatic test pattern generation) system. It is concluded that test generation for I_DDQ faults is quicker and more complete than for equivalent SSF faults, and even without explicit I_DDQ test generation, I _DDQ monitoring can be added to existing SSF testing for increased defect coverage