Title :
CMOS low-VT preamplifier for 0.5-V gigabit-DRAM arrays
Author :
Kotabe, Akira ; Yanagawa, Yoshimitsu ; Akiyama, Satoru ; Sekiguchi, Tomonori
Author_Institution :
Central Res. Lab., Hitachi, Ltd., Kokubunji, Japan
Abstract :
A novel CMOS low-VT preamplifier suitable for low-voltage and high-speed mid-point sensing was developed for gigabit DRAM. This preamplifier consists of a low-VT NMOS cross couple, a low-VT PMOS cross couple and a high-VT CMOS latch. The sensing speed of the proposed preamplifier at data-line voltage of 0.5 V is 62% higher than that of a conventional preamplifier. By activating the low-VT NMOS and PMOS cross couples temporarily during write operation, writing time is 72% shorter compared to the case with the high-VT CMOS latch only. Data-line charging current of a memory cell array with the proposed preamplifier is reduced by 26% by decreasing data-line voltage from 0.8 to 0.5 V.
Keywords :
CMOS memory circuits; DRAM chips; preamplifiers; CMOS low-VT preamplifier; data-line charging current; data-line voltage; gigabit-DRAM arrays; high-VT CMOS latch; high-speed midpoint sensing; low-VT PMOS cross couple; low-VT NMOS cross couple; memory cell array; sensing speed; voltage 0.5 V; write operation; writing time; Laboratories; Latches; MOS devices; Operational amplifiers; Preamplifiers; Random access memory; Solid state circuits; Tin; Voltage; Writing;
Conference_Titel :
Solid-State Circuits Conference, 2009. A-SSCC 2009. IEEE Asian
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-4433-5
Electronic_ISBN :
978-1-4244-4434-2
DOI :
10.1109/ASSCC.2009.5357144
