Title :
A high-frame-rate dense motion vector field generation processor with simplified best-match searching circuitries
Author :
Okano, Yuta ; Shibata, Tadashi
Author_Institution :
Dept. of Frontier Inf., Univ. of Tokyo, Tokyo, Japan
Abstract :
A high-frame-rate dense motion vector field generation processor employing an efficient data manipulation scheme has been developed. The computation result of detecting a motion vector (MV) at each pixel location is reused in the adjacent location. As a result, the size of a best-match searching circuitry for MV detection has been reduced to 1/10 of that without data reuse. This allows us to implement two MV calculation units on a chip without area penalty, enabling dual MV generation at every clock cycle except for the initial period of overhead processing. As a result, the frame rate has been increased by 23% as compared to the previous architecture, while the total number of transistors has been reduced by 41%. A prototype chip was designed and fabricated in a 0.18-¿m 5-metal CMOS technology. It was experimentally demonstrated that the chip can generate motion vectors from all pixel sites of 256Ã256-size motion images at a frame rate of 1060 frames/sec with a clock frequency of 100 MHz.
Keywords :
CMOS digital integrated circuits; clocks; microprocessor chips; MV detection; clock cycle; clock frequency; data manipulation scheme; frequency 100 GHz; high-frame-rate dense motion vector field generation processor; metal CMOS technology; pixel location; size 0.18 mum; transistors; CMOS technology; Circuits; Clocks; Computational efficiency; Humans; Image recognition; Motion detection; Pixel; Vehicle safety; Very large scale integration;
Conference_Titel :
Solid-State Circuits Conference, 2009. A-SSCC 2009. IEEE Asian
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-4433-5
Electronic_ISBN :
978-1-4244-4434-2
DOI :
10.1109/ASSCC.2009.5357145