Integrating boundary scan test into an ASIC design flow

The author describes how boundary scan test (BST) can be integrated into an existing ASIC (application-specific-integrated-circuit) design flow. By use of a library of BST building blocks and a design-for-testability (DFT) compiler, very fast generation of BST circuitry for an ASIC is possible. The DFT compiler will also generate the test patterns needed for testing the BST circuitry and a data sheet fulfilling the documentation requirements. The compilation of a BST circuit for a state-of-the-art ASIC is presented as an example. Additional silicon area overhead, fault coverage, and test length were obtained. Software performance figures are given