Title :
A 439K gates/10.9KB SRAM/2–328 mW dual mode video decoder supporting temporal/spatial scalable video
Author :
Chien, Cheng-An ; Yang, Yao-Chang ; Chang, Hsiu-Cheng ; Guo, Jiun-In ; Chen, Jia-Wei ; Wang, Jinn-Shan ; Wang, Chin-Hsien ; Huang, Hsiang-Hui ; Cheng, Ching-Hwa
Author_Institution :
Dept. of CSIE, Nat. Chung-Cheng Univ., Chiayi, Taiwan
Abstract :
The first dual mode video decoder with 4-level temporal/spatial scalability and 32/64-bit adjustable memory bus width is proposed. A design automation environment of simulation and verification is established to automatically verify the correctness and completeness of the proposed design. Using a 0.13 ¿m CMOS technology, it comprises 439 K gates/10.9 KB SRAM and consumes 2~328 mW in decoding CIF~HD1080 videos at 3.75~30 fps when operating at 1~150 MHz, respectively.
Keywords :
CMOS integrated circuits; SRAM chips; video coding; CIF-HD1080 videos; CMOS technology; SRAM; adjustable memory bus width; dual mode video decoder; frequency 1 MHz to 150 MHz; memory size 10.9 KByte; power 2 mW to 328 mW; size 0.13 mum; temporal-spatial scalable video; CMOS technology; Decoding; Design optimization; High definition video; Random access memory; Scalability; Static VAr compensators; TV; Video coding; Videoconference;
Conference_Titel :
Solid-State Circuits Conference, 2009. A-SSCC 2009. IEEE Asian
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-4433-5
Electronic_ISBN :
978-1-4244-4434-2
DOI :
10.1109/ASSCC.2009.5357147
