Title :
A 250Mb/s-to-3Gb/s 5x oversampling receiver with an all-digital adapting equalizer
Author :
Chou, Min-Chung ; Chen, Qui-Ting ; Chen, Ping
Author_Institution :
MediaTek Inc., Hsinchu, Taiwan
Abstract :
In this paper, a 250 Mb/s-to-3 Gb/s 5x oversampling receiver with an all-digital adapting equalizer is presented. A novel oversampling based inter-symbol interference (ISI) monitor and adapting flows are proposed for the equalizer to compensate channel losses. The receiver has been implemented in 65-nm CMOS process. The analog equalizer has a power consumption of 9.6 mW and an area of 0.012 mm2 including an all-digital ISI monitor and an adapting circuit. The core area of the receiver is 0.26 mm2, including the input terminations, the shared PLL, and three data channels.
Keywords :
CMOS integrated circuits; equalisers; intersymbol interference; phase locked loops; radio receivers; CMOS process; adapting circuit; all digital adapting equalizer; analog equalizer; compensate channel losses; inter-symbol interference monitor; oversampling receiver; power 9.6 mW; radio receiver; shared PLL; size 65 nm; Bandwidth; Boosting; Cables; Circuits; Clocks; Equalizers; Intersymbol interference; Monitoring; Phase locked loops; Timing;
Conference_Titel :
Solid-State Circuits Conference, 2009. A-SSCC 2009. IEEE Asian
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-4433-5
Electronic_ISBN :
978-1-4244-4434-2
DOI :
10.1109/ASSCC.2009.5357151
