Hierarchical test assembly for macro based VLSI design

Author

Leenstra, Jens ; Spaanenburg, Lambert

Author_Institution

Inst. for Microelectron. Stuttgart, West Germany

fYear

1990

fDate

10-14 Sep 1990

Firstpage

520

Lastpage

529

Abstract

A novel incremental procedure for the hierarchical assembly of macro test specifications into a chip test program is presented. To solve test generation/application problems, a bottom-up symbolic test assembly procedure that proceeds in line with the construction of the system is proposed. It is shown that for a modular design approach, this procedure can be extended with design-for-testability features to ensure that all macro tests are assembled into a chip test program. The approach is exemplified by the design of a decimation filter for a Σ/Δ A/D (analog-to-digital) converter

Keywords

VLSI; automatic testing; circuit CAD; integrated circuit testing; modules; VLSI design; analog to digital convertor; automatic testing; bottom-up symbolic test; chip test program; decimation filter; design-for-testability; hierarchical assembly; macro test specifications; macro tests; modular design; Assembly systems; Design automation; Finite impulse response filter; Logic design; Logic gates; Logic testing; Microelectronics; Power generation; System testing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1990. Proceedings., International

Conference_Location

Washington, DC

Print_ISBN

0-8186-9064-X

Type

conf

DOI

10.1109/TEST.1990.114063

Filename

114063