State transition graph analysis as a key to BIST fault coverage

Author

Brynestad, Ove ; Aas, Einar J. ; Vallestad, Anne E.

Author_Institution

Nordic VLSI Inc., Trondheim, Norway

fYear

1990

fDate

10-14 Sep 1990

Firstpage

537

Lastpage

543

Abstract

The authors consider the analysis of the state transition graph (STG) as a key to understanding the state and fault coverage of BIST (built-in self-test) schemes. Some interesting topological properties of STGs are found. These may be exploited when BIST schemes are being designed. Specifically, the problem of limit cycles in STGs is discussed, and ways of defining initial states to yield long paths before state repetition are presented. One BIST scheme that has modest overhead requirements and is based on serial shift registers is given. The scheme is applied to some of the ISCAS-89 benchmark circuits, and experimental results on fault coverage are presented

Keywords

built-in self test; directed graphs; fault location; logic testing; shift registers; BIST fault coverage; ISCAS-89 benchmark circuits; built-in self-test; initial states; limit cycles; logic testing; serial shift registers; state transition graph; Automata; Benchmark testing; Built-in self-test; Circuit faults; Circuit testing; Limit-cycles; Logic testing; Registers; Tin; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1990. Proceedings., International

Conference_Location

Washington, DC

Print_ISBN

0-8186-9064-X

Type

conf

DOI

10.1109/TEST.1990.114065

Filename

114065