An 8 Gbps fast-locked automatic gain control for PAM receiver

Author

Wu, Guo Wei ; Chen, Wei Zen ; Huang, Shih Hao

Author_Institution

Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

fYear

2009

fDate

16-18 Nov. 2009

Firstpage

173

Lastpage

176

Abstract

An 8 Gbps automatic gain control (AGC) loop for PAM receiver is proposed. Incorporating digital intensive gain control scheme, the dynamic range of the variable gain amplifier is 22 dB with a resolution of 0.9 dB/step. The locking time of the AGC loop is less than 200 ns and independent of input amplitude. Fabricated in a 0.18 Â¿m CMOS technology, the chip size is 0.62 mm Ã— 0.62 mm. The total power dissipation is 84 mW from a 1.8 V supply.

Keywords

CMOS digital integrated circuits; amplification; automatic gain control; optical receivers; pulse amplitude modulation; CMOS technology; PAM receiver; bit rate 8 Gbit/s; digital intensive gain control scheme; dynamic range; fast-locked automatic gain control loop; gain 22 dB; total power dissipation; variable gain amplifier; Bandwidth; CMOS technology; Detectors; Digital control; Dual band; Gain control; Optical amplifiers; Optical fiber communication; Optical receivers; Voltage control; PAM receiver; automatic gain control (AGC); variable gain amplifier;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2009. A-SSCC 2009. IEEE Asian

Conference_Location

Taipei

Print_ISBN

978-1-4244-4433-5

Electronic_ISBN

978-1-4244-4434-2

Type

conf

DOI

10.1109/ASSCC.2009.5357153

Filename

5357153