A 5Gb/s low-power PCI express/USB3.0 ready PHY in 40nm CMOS technology with high-jitter immunity

Author

Lin, Mu Shan ; Tsai, Chien Chun ; Chang, Chih Hsien ; Peng, Yung Chow ; Tsung-Hsin Yu ; Chien, Jinn Yeh ; Chen, W.D. ; Lu, Chi Chang ; Chen, Wei Chih ; Fu, Jimmy ; Yang, S.J. ; Chen, Chien Hung ; Deng, Kuo Liang ; Wen, C.H. ; Wang, L.Y.

Author_Institution

HSCD/DTP, Taiwan Semicond. Manuf. Co., Ltd., Hsinchu, Taiwan

fYear

2009

fDate

16-18 Nov. 2009

Firstpage

177

Lastpage

180

Abstract

A PCI Express 2.0/1.0 compatible SERDES system had been fabricated in TSMC 40 nm CMOS technology. With the implementation of one lane transceiver, PLL, and PCS, the experimental results have shown this test chip passes PCI Express 2.0/1.0 TX compliance test and RX compliance test. It also achieves receiver jitter tolerance up to 0.33UI at BER of 10^-12 with stressing all spec. specified jitter sources. A compact area of 510 um * 710 um for one lane has been achieved while consuming only 125 mW from 0.9 V supply.

Keywords

CMOS integrated circuits; clock and data recovery circuits; conformance testing; driver circuits; equalisers; feedforward; integrated circuit testing; peripheral interfaces; phase locked loops; radiofrequency integrated circuits; timing jitter; transceivers; PCI Express 2.0/1.0 RX compliance test; PCI Express 2.0/1.0 TX compliance test; PCS; PLL; RX linear equalizer; TSMC CMOS technology; TX De-emphasis Driver; bit rate 5 Gbit/s; clock and data recovery circuit; compatible SERDES system; feed-forward equalization; high-jitter immunity; jitter sources; low-power PCI Express ready PHY; low-power USB 3.0 ready PHY; one lane transceiver; power 125 mW; serializer-deserializer; size 40 nm; voltage 0.9 V; Bit error rate; CMOS technology; Clocks; Equalizers; Jitter; Personal communication networks; Phase locked loops; Physical layer; Testing; Transceivers; Deterministic jitter; Inter-symbol-interference; Random jitter; Serializer-Deserializer; clock and data recovery; total jitter;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2009. A-SSCC 2009. IEEE Asian

Conference_Location

Taipei

Print_ISBN

978-1-4244-4433-5

Electronic_ISBN

978-1-4244-4434-2

Type

conf

DOI

10.1109/ASSCC.2009.5357154

Filename

5357154