A delay-locked loop with digital background calibration

A delay-locked loop (DLL) with digital background calibration is presented. The static phase error of a DLL may exist owing to the current mismatch in the charge pump (CP). A digital background calibration using the time amplifier is presented. This DLL is fabricated in a CMOS 0.18 ¿m technology. The measured input frequency range of this DLL is from 400 MHz to 525 MHz. The measured static phase error without and with calibration is 113.8 ps and 27.8ps, respectively, at 525 MHz. The measured peak-to-peak jitter without and with calibration is 15.56 ps and 15.11 ps, respectively. The power consumption is 25.2 mW at 500 MHz and the area is 0.85 mm².