An integrated linear regulator with fast output voltage transition for SRAM yield improvement

This work presents a fully integrated linear regulator design that can dynamically assign the SRAM cell voltage to increase the read/write margin. To minimize the timing overhead between read/write mode switches, this design adopts two separate feedback loops for bias and load regulations. Individual optimization for each loop makes fast reference tracking and load regulation possible. To verify this concept, a prototype LDO is realized with a 1.8-V 0.18 ¿m CMOS. The output voltage can be freely set between 0.9 and 1.7-V. The measured transition speed is 48 ns/0.3 V. The maximum current efficiency is 94.7% under a 20 mA current loading.