• DocumentCode
    2723715
  • Title

    Optimized testing of meshes

  • Author

    Malek, Miroslaw ; Özden, Banu

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
  • fYear
    1990
  • fDate
    10-14 Sep 1990
  • Firstpage
    627
  • Lastpage
    637
  • Abstract
    Efficient testing techniques for two-dimensional mesh interconnection networks are presented. The tests cover faults in the data paths and the control circuitry, including faults in the arbitration logic of the switches. Testing for the resolution of the conflicts is important for ensuring the correct functioning of the interconnection network, since a fault in the arbitration logic may cause the loss of packets. Modeling conflict resolution as a graph coloring the approach optimizes the testing time by parallelizing the tests for different nodes. The testing time is constant, independent of the size of the parallel network, except for the routing tests. The proposed methods are not implementation specific and can be applied to any design with a mesh topology. However, for some specific designs only a subset of tests might be needed, depending on the type of communication or control scheme. The novel approach to the minimization of the conflict tests is twofold: it can be used to test the conflicts; it also gives a method for controlling each input of a switch and observing each output of the switch such that any test at each level can be applied to as many nodes as possible simultaneously
  • Keywords
    automatic testing; computer testing; graph colouring; logic testing; multiprocessor interconnection networks; network topology; parallel architectures; arbitration logic; computer testing; conflict tests; control circuitry; data paths; graph coloring; mesh topology; parallel network; testing time; two-dimensional mesh interconnection networks; Circuit faults; Circuit testing; Communication switching; Communication system control; Logic circuits; Logic testing; Multiprocessor interconnection networks; Routing; Switches; Switching circuits;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Conference, 1990. Proceedings., International
  • Conference_Location
    Washington, DC
  • Print_ISBN
    0-8186-9064-X
  • Type

    conf

  • DOI
    10.1109/TEST.1990.114077
  • Filename
    114077