Title :
Computer-aided design of pseudoexhaustive BIST for semiregular circuits
Author :
Su, Chau-Chin ; Kime, Charles R.
Author_Institution :
Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan
Abstract :
The authors propose a special class of hierarchy, the sensitizable hierarchy, to handle simultaneously both circuit partitioning and test pattern delivery for pseudoexhaustive BIST (built-in self-test). Instead of developing specialized tools for different cases in an unsensitizable hierarchy, they attempt to reconstructure the hierarchy to make it sensitizable. In order to verify the sensitizability of a hierarchy and restructure an unsensitizable hierarchy, the authors study the characteristics of hierarchical circuits and conclude that there are three usable semiregular properties, namely, the separation of data and control signals, the availability of functional units and functional descriptions, and frequent use of array structure. On the basis of these properties, the following are derived: a structure recognition process to identify the implicit array and functional unit structure; a hierarchical, multilevel, multiple-path sensitization algorithm to sensitize paths for test application and response observation; a restructuring process to obtain a sensitizable hierarchy; and a straightforward procedure for pseudoexhaustive BIST for a sensitizable hierarchy. All of these processes and procedures use a common knowledge base and are integrated by use of a frame-based system implemented with Franz Lisp
Keywords :
automatic testing; built-in self test; knowledge based systems; logic CAD; logic testing; CAD; Franz Lisp; array structure; built-in self-test; circuit partitioning; frame-based system; functional unit structure; hierarchical multilevel algorithm; implicit array; knowledge base; multiple-path sensitization algorithm; pseudoexhaustive BIST; restructuring process; semiregular circuits; sensitizable hierarchy; structure recognition; test pattern delivery; Built-in self-test; Character generation; Circuit faults; Circuit testing; Combinational circuits; Degradation; Design automation; Hardware; Sequential analysis; Sequential circuits;
Conference_Titel :
Test Conference, 1990. Proceedings., International
Conference_Location :
Washington, DC
Print_ISBN :
0-8186-9064-X
DOI :
10.1109/TEST.1990.114083