DocumentCode :
2723807
Title :
High frequency measurements and simulations on wire-bonded modules on the sequential build-up boards (SBU)
Author :
Sihlbom, Rolf ; Dernevik, Markus ; Lindgren, Mats ; Starski, Piotr ; Lai, Zonghe ; Liu, Johan
Author_Institution :
IVF, Molndal, Sweden
fYear :
1997
fDate :
26-30 Oct 1997
Firstpage :
131
Lastpage :
139
Abstract :
This paper gives results from HF measurements and simulation of sequential build-up boards (SBU). An HF test pattern was designed to investigate SBU HF properties. SBUs were supplied by four manufacturers. The test SBUs contained patterns for crosstalk, impedance matching, stray capacitance and wire bonding. The boards had a double-sided FR-4 core with two built-up layers on each side, but the HF test board was only on one side. Test patterns were located in layers five and six. Two line spacings between signal and victim tracks of 50 μm and 100 μm were considered. S-parameters were measured on a network analyser in the 45 MHz-10 GHz range. In time domain test, near-end and far-end responses were measured. Simulations used P-SPICE, HP MDS and a 2D finite difference program. Impedance measurements and simulations were performed in layers five and six with conductor widths for 50 Ω and 55 Ω characteristic impedances. Line widths ranged from 40-65 μm in layer five and 150-200 μm in layer six. Reference tracks were designed to estimate conductor and dielectric loss. In the wire-bonding test, two interconnect types were assessed: a solder joint and an isotropically conductive adhesive joint (ICA). A Si test chip was used for wire-bonding on the SBU-board. Crosstalk measurements and simulations agreed closely over 45 MHz-10 GHz. Small differences between the three dielectrics were obtained, and dielectric loss is a limiting factor in the HF range. For a test pattern length of 30 mm, the HF limit (-3 dB transmission loss), was 2-3 GHz in layer six and 3-4 GHz in layer five. Measured characteristic impedances ranged from 44-63 Ω
Keywords :
S-parameters; SPICE; adhesion; assembling; conducting polymers; dielectric losses; dielectric thin films; electric impedance; filled polymers; finite difference methods; impedance matching; lead bonding; modules; packaging; printed circuit testing; soldering; 2D finite difference program; HF measurements; HF simulation; HF test board; HF test pattern; HP MDS simulation; P-SPICE simulation; S-parameters; SBU HF properties; SBU-board; Si test chip; built-up layers; characteristic impedance; conductor loss; crosstalk; dielectric loss; double-sided FR-4 core; far-end response; high frequency measurements; high frequency simulations; impedance matching; impedance measurements; impedance simulation; interconnect types; isotropically conductive adhesive joint; line spacings; line width; near-end response; network analyser; sequential build-up boards; signal tracks; solder joint; stray capacitance; test SBUs; test pattern length; test patterns; time domain test; transmission loss; victim tracks; wire bonding; wire-bonded modules; wire-bonding; wire-bonding test; Conductors; Crosstalk; Dielectric losses; Dielectric measurements; Frequency measurement; Hafnium; Impedance matching; Impedance measurement; Manufacturing; Testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Polymeric Electronics Packaging, 1997. Proceedings., The First IEEE International Symposium on
Conference_Location :
Norrkoping
Print_ISBN :
0-7803-3865-0
Type :
conf
DOI :
10.1109/PEP.1997.656483
Filename :
656483
Link To Document :
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