Parallel pattern fault simulation based on stem faults in combinational circuits

Significant improvements in the speed of fault simulation of combinational circuits have been achieved by combining parallel pattern simulation of the fault-free circuit with tracing-based methods for identifying detected faults. The authors propose a method of reducing the expense of backtracing by identifying lines where backtracking may be stopped, and they show its efficiency through an experiment with a set of benchmark circuits. The proposed method has been implemented in the C language on a VAX 6210/VMS which has a machine word of 32 b. Thirty-two patterns are processed in parallel during true-value simulation, backtracing, and stem analysis. Calculations of the sensitivity, stem-criticality, and checkup vectors are performed by vector operations when each line is reached during first backtracing. The results indicate that the proposed method is more efficient than that of K.J. Antreich and M.H. Schultz (1987) for all the benchmark circuits that were simulated