AC product defect level and yield loss

Author

Savir, Jacob

Author_Institution

IBM Corp., Poughkeepsie, NY, USA

fYear

1990

fDate

10-14 Sep 1990

Firstpage

726

Lastpage

738

Abstract

The author considers the AC defect level and yield loss after test for both logic and random-access-memory semiconductor chips. Computation of chip AC defect level and yield loss after test is dependent upon the availability of statistical information regarding the behavior of the chip´s delay and of the tester error. This statistical information can either be derived from manufacturing process parameters or measured by a tester. It is shown that there is a relationship between the chip-shipped defect level and the yield loss after test. Thus, a change in one will, in general, affect the other

Keywords

electronic engineering computing; integrated circuit testing; integrated logic circuits; integrated memory circuits; probability; production testing; random-access storage; statistical analysis; AC product defect level; RAM; availability; chip-shipped defect level; delay; manufacturing process; random-access-memory semiconductor chips; statistical analysis; tester error; yield loss; Added delay; Automatic testing; Circuit faults; Circuit testing; Costs; Delay effects; Logic testing; Page description languages; Semiconductor device packaging; Semiconductor device testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1990. Proceedings., International

Conference_Location

Washington, DC

Print_ISBN

0-8186-9064-X

Type

conf

DOI

10.1109/TEST.1990.114089

Filename

114089