Testability features of the 68040

Author

Gallup, Michael G. ; Ledbetter, William, Jr. ; McGarity, Ralph ; McMahan, Steve ; Scheuer, Kenneth C. ; Shepard, Clark G. ; Sood, Lal

Author_Institution

Motorola Inc., Austin, TX, USA

fYear

1990

fDate

10-14 Sep 1990

Firstpage

749

Lastpage

757

Abstract

The design and implementation of on-chip test functions on the 68040 microprocessor are described. The discussion includes an introduction to the 68040, along with the testability goals and objectives that were set at the beginning of the design. Further discussions detail the different design-for-testability techniques used to control and observe the behavior of the 68040 subsystems. Topics covered include the global test architecture, special test modes for the internal RAM arrays, the scan circuitry used for structural testing of random logic, and the IEEE 1149.1 (JTAG) implementation on the 68040

Keywords

computer architecture; integrated circuit testing; integrated memory circuits; logic arrays; logic testing; microprocessor chips; printed circuit testing; production testing; random-access storage; 68040 microprocessor; IEEE 1149.1 JTAG; cache test; global test architecture; internal RAM arrays; on-chip test functions; random logic; scan circuitry; scan test; structural testing; testability; Automatic testing; Circuit testing; Design for testability; Logic arrays; Logic testing; Microprocessors; Phase locked loops; Read-write memory; Registers; Software testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1990. Proceedings., International

Conference_Location

Washington, DC

Print_ISBN

0-8186-9064-X

Type

conf

DOI

10.1109/TEST.1990.114091

Filename

114091