A gated ring oscillator based parallel-TDC system with digital resolution enhancement

Author

Vengattaramane, Kameshwaran ; Borremans, Jonathan ; Steyaert, Michiel ; Craninckx, Jan

Author_Institution

SSET, IMEC, Leuven, Belgium

fYear

2009

fDate

16-18 Nov. 2009

Firstpage

57

Lastpage

60

Abstract

A digital resolution enhancement technique for time-to-digital converters (TDC) is proposed. This involves a simultaneous multi-channel measurement of a time-interval with low-complexity TDCs of varying resolutions. The coarse outputs of each converter are then digitally post-processed to obtain a single result whose precision is much better than that of any individual converter. A prototype system with 8 channels is demonstrated in 90-nm CMOS. 45 MS/s output of each channel is algorithmically combined to obtain over 2-3X improvement in the resolution in 4/6/8 channel modes. The chip occupies 0.3 mm² and draws up to a maximum of 4 mA from a 1.2 V supply.

Keywords

CMOS digital integrated circuits; analogue-digital conversion; oscillators; time measurement; CMOS; current 4 mA; digital post-processing; digital resolution enhancement; gated ring oscillator; parallel-TDC system; simultaneous multi-channel measurement; size 90 nm; time interval; time-to-digital converters; voltage 1.2 V; Analog circuits; Delay effects; Delay lines; Frequency synthesizers; Interpolation; Inverters; Phase locked loops; Phase measurement; Quantization; Ring oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2009. A-SSCC 2009. IEEE Asian

Conference_Location

Taipei

Print_ISBN

978-1-4244-4433-5

Electronic_ISBN

978-1-4244-4434-2

Type

conf

DOI

10.1109/ASSCC.2009.5357178

Filename

5357178