Title :
A 5GHz 90-nm CMOS all digital phase-locked loop
Author :
Lu, Ping ; Sjöland, Henrik
Author_Institution :
Dept. of Electr. & Inf. Technol., Lund Univ., Lund, Sweden
Abstract :
An all digital phase-locked loop (ADPLL) has been implemented in a 90-nm CMOS process. It uses a phase frequency detector (PFD) connected to two time-to-digital converters (TDC). To save power the TDCs use uneven delay time in the delay line cells. An automatic tuning bank controller selects active bank of the digitally controlled oscillator (DCO), which features three separate tuning banks. The PLL achieves a phase noise of -125 dBc/Hz at 1 MHz offset from a divided-by-2 carrier frequency of 2.58 GHz. The core area is 0.33 mm2 and the current consumption is 30 mA from a 1.2 V supply.
Keywords :
CMOS integrated circuits; phase locked loops; phase noise; CMOS process; automatic tuning bank controller; current 30 mA; current consumption; delay line cells; digital phase-locked loop; digitally controlled oscillator; divided-by-2 carrier frequency; frequency 1 MHz to 5 GHz; phase frequency detector; phase noise; size 90 nm; time-to-digital converters; uneven delay time; voltage 1.2 V; Automatic control; CMOS process; Delay effects; Delay lines; Digital control; Oscillators; Phase frequency detector; Phase locked loops; Phase noise; Tuning;
Conference_Titel :
Solid-State Circuits Conference, 2009. A-SSCC 2009. IEEE Asian
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-4433-5
Electronic_ISBN :
978-1-4244-4434-2
DOI :
10.1109/ASSCC.2009.5357180
