DocumentCode
2724011
Title
Why is less information from logic simulation more useful in fault simulation?
Author
Akers, Sheldon B. ; Park, Sungju ; Krishnamurthy, Balakrishnan ; Swaminathan, Ashok
Author_Institution
Massachusetts Univ., Amherst, MA, USA
fYear
1990
fDate
10-14 Sep 1990
Firstpage
786
Lastpage
800
Abstract
The authors propose a novel linear-time algorithm for identifying, in a large combinatorial circuit, a large set of faults that are undetectable by a given test vector. Although this so-called X-algorithm does not identify all the undetectable faults, empirical evidence is offered to show that the reduction in the number of remaining faults to be simulated is significant. The algorithm is intended as a simple, fast preprocessing step to be performed after a test vector has been generated, but before the (often lengthy) process of fault simulation begins. The empirical results indicate that the X-algorithm is both useful (indicated by the utility factor) and good (indicated by the effectiveness factor). It provides as much as a 50% reduction in the number of faults that need to be simulated. Moreover, the algorithm seems to identify a large fraction of the undetectable faults
Keywords
combinatorial circuits; fault location; logic testing; performance evaluation; X-algorithm; combinatorial circuit; fault location; fault simulation; linear-time algorithm; logic simulation; preprocessing; test vector; Circuit faults; Circuit simulation; Circuit testing; Combinational circuits; Context modeling; Fault detection; Fault diagnosis; Logic; Performance evaluation; Test pattern generators;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 1990. Proceedings., International
Conference_Location
Washington, DC
Print_ISBN
0-8186-9064-X
Type
conf
DOI
10.1109/TEST.1990.114096
Filename
114096
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