Title :
A 65nm CMOS 3.6GHz fractional-N PLL with 5th-order ΔΣ modulation and weighted FIR filtering
Author :
Yu, Xueyi ; Sun, Yuanfeng ; Rhee, Woogeun ; Ko, Sangsoo ; Choo, Wooseung ; Park, Byeong Ha ; Wang, ZhiHua
Author_Institution :
Inst. of Microelectron., Tsinghua Univ., Beijing, China
Abstract :
A 3.6 GHz fractional-N PLL utilizing high-order digital modulation and weighted 13-tap finite impulse response (FIR) filtering for low spur and enhanced noise reduction is implemented in 65 nm CMOS. The prototype PLL exhibits nearly -100 dBc/Hz in-band noise contribution and -126.8 dBc/Hz phase noise at a 3 MHz offset from a 1.8 GHz carrier. With 5th-order single-loop ΔΣ modulation, the fractional spur levels of -65.6 dBc and -58.5 dBc are achieved within the bandwidth and near the bandwidth, respectively.
Keywords :
CMOS integrated circuits; FIR filters; delta-sigma modulation; integrated circuit noise; phase locked loops; phase noise; 5th-order single-loop ΔΣ modulation; CMOS fractional-N PLL; finite impulse response filtering; fractional spur level; frequency 1.8 GHz; frequency 3.6 GHz; high-order digital modulation; in-band noise; noise reduction; phase noise; size 65 nm; weighted FIR filtering; 1f noise; Bandwidth; Digital filters; Digital modulation; Filtering; Finite impulse response filter; Noise reduction; Phase locked loops; Phase noise; Prototypes;
Conference_Titel :
Solid-State Circuits Conference, 2009. A-SSCC 2009. IEEE Asian
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-4433-5
Electronic_ISBN :
978-1-4244-4434-2
DOI :
10.1109/ASSCC.2009.5357183
