A novel built-in self-repair approach to VLSI memory yield enhancement

Author

Mazumder, P. ; Yih, J.S.

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA

fYear

1990

fDate

10-14 Sep 1990

Firstpage

833

Lastpage

841

Abstract

The feasibility of implementing electronic neural networks as intelligent hardware for memory array repair is demonstrated. In particular, it is shown that the neural network control possesses a robust and degradable computing capability under various fault conditions. A yield analysis performed on 64K DRAMs shows that the yield can be improved from as low as 20% to near 99% owing to the self-repair design, with an overhead of no more than 7%. Simulation shows that the neural net algorithms are superior to the Repair Most algorithm

Keywords

DRAM chips; VLSI; built-in self test; digital simulation; electronic engineering computing; integrated circuit testing; integrated memory circuits; maintenance engineering; neural nets; optimisation; 64×10³ bit; DRAMs; Hill Climbing algorithm; VLSI memory yield enhancement; built-in self-repair; combinatorial optimisation; degradable computing capability; digital simulation; intelligent hardware; neural networks; overhead; yield analysis; Built-in self-test; Circuit faults; Fault diagnosis; Fault tolerance; Hardware; Neural networks; Optical arrays; Software algorithms; Throughput; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1990. Proceedings., International

Conference_Location

Washington, DC

Print_ISBN

0-8186-9064-X

Type

conf

DOI

10.1109/TEST.1990.114101

Filename

114101