• DocumentCode
    2724179
  • Title

    Built-in self-test in a 24 bit floating point digital signal processor

  • Author

    Sakashita, Narumi ; Sawai, Hisako ; Teraoka, Eiichi ; Fujiyama, Toshiki ; Kengaku, Toru ; Shimazu, Yukihiko ; Tokuda, Takeshi

  • Author_Institution
    Mitsubishi Electr. Corp., Hyogo, Japan
  • fYear
    1990
  • fDate
    10-14 Sep 1990
  • Firstpage
    880
  • Lastpage
    885
  • Abstract
    The authors describe a built-in self-test (BIST) method implemented in a 24-b floating-point digital signal processor (DSP) using pseudorandom patterns. By use of only one pair- of LFSRs (linear feedback shift registers) and 253 words of normal instruction, 95% of the functional blocks are self-tested. The number of the test vectors is 35 million. However, the entire BIST takes only 2.6 s for the test, owing to the fast machine cycle time of 75 ns. The overhead of the test hardware is only 2.0% of the die size. The evaluation results show that a BIST is very useful for computationally intensive VLSI processors, such as a DSP
  • Keywords
    VLSI; built-in self test; digital signal processing chips; integrated circuit testing; logic testing; shift registers; 24 bit; BIST; IC testing; VLSI; built-in self-test; floating point digital signal processor; linear feedback shift registers; pseudorandom patterns; test vectors; Arithmetic; Automatic testing; Built-in self-test; Costs; Digital signal processing; Digital signal processing chips; Digital signal processors; Large scale integration; Research and development; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Conference, 1990. Proceedings., International
  • Conference_Location
    Washington, DC
  • Print_ISBN
    0-8186-9064-X
  • Type

    conf

  • DOI
    10.1109/TEST.1990.114106
  • Filename
    114106