Sub-micron chip ESD protection schemes which avoid avalanching junctions

Because of leakage problems related to avalanche breakdown of salicided junctions, an array of ESD protection methods has been developed and tested which depend on forward biased diodes and normal MOSFET conduction. These methods include the case of multiple power supplies, the case where the pad voltage can exceed the power supply voltage, and the case where the pad voltage both exceeds the power supply voltage and the process voltage limit. These methods result in parts made in 0.8 and 0.6 /spl mu/m salicided technologies routinely passing our upper division spec. of /spl plusmn/4500 V HBM without any discernible increase in pin leakage. Also, split supply salicided parts pass 1 kV of CDM with no discernible pin leakage increase and 2 kV with pin leakage increase but within spec. (10 /spl mu/A).