Title :
A 6bit, 7mW, 250fJ, 700MS/s subranging ADC
Author :
Asada, Yusuke ; Yoshihara, Kei ; Urano, Tatsuya ; Miyahara, Masaya ; Matsuzawa, Akira
Author_Institution :
Dept. of Phys. Electron., Tokyo Inst. of Technol., Tokyo, Japan
Abstract :
A 6 bit, 7 mW, 700 MS/s subranging ADC fabricated in 90 nm CMOS technology with SNDR of 34 dB for Nyquist input frequency is presented. The subranging architecture using CDACs, gate-weighted interpolation scheme, and digitally offset calibrating double-tail latched comparators has demonstrated an ultra low FoM of 250 fJ/conv. steps. and attractiveness for embedded IP for low power SoCs.
Keywords :
CMOS integrated circuits; analogue-digital conversion; calibration; comparators (circuits); flip-flops; integrated circuit noise; interpolation; CDAC; CMOS technology; Nyquist input frequency; SNDR; digitally offset calibration; double-tail latched comparator; embedded IP; gate-weighted interpolation method; low power SoC; power 7 mW; size 90 nm; subranging ADC; ultralow FoM; word length 6 bit; CMOS technology; Energy consumption; Frequency conversion; Interpolation; Power dissipation; Power generation; Resistors; Solid state circuits; Timing; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 2009. A-SSCC 2009. IEEE Asian
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-4433-5
Electronic_ISBN :
978-1-4244-4434-2
DOI :
10.1109/ASSCC.2009.5357198
