A low supply voltage operation SRAM with HCI trimmed sense amplifiers

This paper proposes a new scheme utilizing a small offset voltage (Vos) sense amplifier (SA) to reduce the deterioration of the read speed and the cell stability at the low power supply. This concept is introduced to realize a low supply voltage operation SRAM with a small area penalty. The transistor threshold voltage (Vth) shift caused by hot carrier injection (HCI) is used for Vos trimming after the chip fabrication. The SA with the offset trimming circuit is implemented in 40 nm CMOS technology and the reduction of Vos by 76 mV has been confirmed with the measurement and simulation results. This reduction corresponds to the improvement of read frequency by 40% and 8× failure rate improvements at 0.6 V supply voltage.