An 8Gb/s/link, 6.5mW/Gb/s memory interface with bimodal request bus

An 8 Gb/s/link power optimized controller memory interface is implemented in TSMC 40 nm G CMOS process. It is composed of 32 differential data links to support 32 GB/s payload. The bimodal drivers of the request bus enable support of both 12 bits of 2 Gb/s/link single-ended RSL (rambus signaling level) for existing XDR^TM memory and 6 bits of 8 Gb/s/link differential signaling for next generation XDR2^TM memory. A 1-tap pre-emphasis transmitter equalizer and a source-degenerated linear receiver equalizer with offset trim are added on this controller interface to reduce signal swing and thus minimize power in both write and read directions. The measurement results show that with a 100 mV swing (peak-to-peak single-ended) for the read and a 150 mV swing for the write, the timing margin is greater than 0.25 UI at a BER of 10^-12 with real memory transactions. The measured power efficiency for the PHY is 6.5 mW/Gb/s.