Analysis of snubber-clamped diode-string mixed voltage interface ESD protection network for advanced microprocessors

Author

Voldman, Steven H. ; Gerosa, G. ; Gross, V.P. ; Dickson, Vaughn P. ; Furkay, Stephen ; Slinkman, James

Author_Institution

Microelectron. Div., IBM Corp., Essex Junction, VT, USA

fYear

1995

fDate

12-14 Sept. 1995

Firstpage

43

Lastpage

61

Abstract

A novel snubber-clamped diode-string ESD protection circuit for mixed voltage interface microprocessor applications is described. Analytical models, circuit simulation, electrical characterization, ESD electrothermal simulation, ESD test data, and an ESD analytical failure model are shown for shallow trench isolation (STI) and LOCOS CMOS technologies.

Keywords

CMOS digital integrated circuits; circuit analysis computing; electrostatic discharge; failure analysis; integrated circuit layout; integrated circuit modelling; isolation technology; microprocessor chips; protection; snubbers; thermal analysis; ESD analytical failure model; ESD electrothermal simulation; ESD protection network; ESD test data; LOCOS CMOS technologies; circuit simulation; diode-string type; electrical characterization; microprocessor applications; mixed voltage interface; shallow trench isolation; snubber-clamped configuration; Analytical models; CMOS technology; Circuit simulation; Circuit testing; Diodes; Electrostatic discharge; Electrothermal effects; Microprocessors; Protection; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Overstress/Electrostatic Discharge Symposium Proceedings, 1995

Conference_Location

Phoenix, AZ, USA

Print_ISBN

1-878303-59-7

Type

conf

DOI

10.1109/EOSESD.1995.478267

Filename

478267