A micro-network on chip with 10-Gb/s transmission link

Author

Liu, Wei-Chang ; Lin, Chih-Hsien ; Jou, Shyh-Jye ; Lu, Hung-Wen ; Su, Chau-Chin ; Hong, Kai-Wei ; Cheng, Kuo-Hsing ; Yang, Shyue-Wen ; Sheu, Ming-hwa

Author_Institution

Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

fYear

2009

fDate

16-18 Nov. 2009

Firstpage

277

Lastpage

280

Abstract

In this paper, a micro-network on chip (MNoC) with 10-Gb/s transmission link is proposed. A prototype system with two 5-port packet-based on-chip micro-switches and a 10-Gb/s data transceiver with an all digital data recovery circuit and a self-calibration clock generator are designed. This chip is implemented in 0.13 Â¿m CMOS technology. The core area of this chip is 990 Â¿m*1600 Â¿m and the power consumption is 155 mW (60 mW for micro-switches and 95 mW for 10-Gb/s data transceiver) at 1.2 V supply voltage with 10-Gb/s transmission data rate.

Keywords

CMOS integrated circuits; calibration; clocks; microswitches; network-on-chip; radio links; transceivers; 5-port packet-based on-chip microswitch prototype system; CMOS technology; MNoC switch; all digital data recovery circuit; bit rate 10 Gbit/s; data transceiver; micronetwork on chip; power 155 mW; power 60 mW; power 95 mW; self-calibration clock generator; size 0.13 mum; size 1600 mum; size 990 mum; transmission link; voltage 1.2 V; CMOS technology; Circuits; Clocks; Energy consumption; Microswitches; Prototypes; System-on-a-chip; Transceivers; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2009. A-SSCC 2009. IEEE Asian

Conference_Location

Taipei

Print_ISBN

978-1-4244-4433-5

Electronic_ISBN

978-1-4244-4434-2

Type

conf

DOI

10.1109/ASSCC.2009.5357256

Filename

5357256