An experimental analog CMOS self-learning chip

Author

Bo, G.M. ; Caviglia, D.D. ; Chiblè, H. ; Valle, M.

Author_Institution

Dept. of Biophys. & Electron. Eng., Genoa Univ., Italy

fYear

1999

fDate

1999

Firstpage

135

Lastpage

139

Abstract

The analog VLSI implementation of an on-chip learning neural network is discussed in this paper. The multi layer perceptron paradigm and back propagation learning rule have been mapped onto analog circuits. A local learning rate adaptation rule has been also considered to improve the training performance (i.e., fast convergence speed). Experimental results confirm the chip functionality and the soundness of our approach

Keywords

CMOS analogue integrated circuits; VLSI; analogue processing circuits; backpropagation; multilayer perceptrons; neural chips; unsupervised learning; analog CMOS self-learning chip; analog VLSI implementation; back propagation learning rule; fast convergence speed; functionality; local learning rate adaptation rule; multi layer perceptron paradigm; neural network; training performance; Analog circuits; Artificial neural networks; Chip scale packaging; Computer networks; Concurrent computing; Energy consumption; Feeds; Hip; Neurons; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics for Neural, Fuzzy and Bio-Inspired Systems, 1999. MicroNeuro '99. Proceedings of the Seventh International Conference on

Conference_Location

Granada

Print_ISBN

0-7695-0043-9

Type

conf

DOI

10.1109/MN.1999.758856

Filename

758856