A PCI bus based correlation matrix memory and its application to k-NN classification

Author

Zhou, Ping ; Austin, Jim

Author_Institution

Dept. of Comput. Sci., York Univ., UK

fYear

1999

fDate

1999

Firstpage

196

Lastpage

204

Abstract

This paper describes a PCI bus based implementation of a binary correlation matrix memory (CMM) neural network and its application and performance for use as a k-NN based pattern classification system. The system expands on earlier VME based systems incorporating FPGA based implementation through greater integration and lower cost. Experimental results for several benchmarks show that, compared with a simple k-NN method, the CMM hardware gave speed up of 8-98.8 times during recall process with a classification performance which is 99%-100% that of a conventional k-NN implementation

Keywords

correlation methods; field programmable gate arrays; neural chips; pattern classification; CMM neural network; PCI bus; binary correlation matrix memory; k-NN classification; pattern classification system; recall process; Application software; Associative memory; Computer architecture; Computer science; Coordinate measuring machines; Costs; Field programmable gate arrays; Hardware; Neural networks; Pattern classification;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics for Neural, Fuzzy and Bio-Inspired Systems, 1999. MicroNeuro '99. Proceedings of the Seventh International Conference on

Conference_Location

Granada

Print_ISBN

0-7695-0043-9

Type

conf

DOI

10.1109/MN.1999.758864

Filename

758864