Perspective on Power IC technology: From design lab to wafer fab

Author

Igic, P. ; Elwin, M.P. ; Holland, P.M.

Author_Institution

Sch. of Eng., Swansea Univ., Swansea, UK

fYear

2010

fDate

16-19 May 2010

Firstpage

73

Lastpage

77

Abstract

A case study regarding development of a 100V Power IC technology is presented in this paper. A combination of conventional cross sectional process and device simulations combined with top down and 3D device simulations have been used to design and optimise the integration of a 100V Lateral DMOS (LDMOS) device for high side bridge applications. This combined simulation approach can streamline the device design process and gain important information about end effects which are lost from 2D cross sectional simulations. Design solutions to negate detrimental end effects are proposed and optimised by top down and 3D simulations and subsequently proven on tested silicon. Different electrical isolation schemes have also been investigated.

Keywords

CMOS integrated circuits; circuit simulation; integrated circuit design; power integrated circuits; 2D cross sectional simulation; 3D device simulation; design lab; device design process; high side bridge application; lateral DMOS; power IC technology; wafer fab; CMOS technology; Consumer electronics; Costs; Design optimization; Isolation technology; Manufacturing processes; Power integrated circuits; Power transistors; Silicon on insulator technology; Thermal conductivity;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics Proceedings (MIEL), 2010 27th International Conference on

Conference_Location

Nis

Print_ISBN

978-1-4244-7200-0

Type

conf

DOI

10.1109/MIEL.2010.5490529

Filename

5490529