Voltage scaling limitations and challenges of memory-rich nanoscale CMOS LSIs

The minimum operating voltage, V_min, of memory-rich nanoscale CMOS LSIs is investigated to open the door to the below 0.5-V era. A new method using speed variation is proposed to evaluate V_min. It shows that V_min is very sensitive to the threshold-voltage variations, ΔV_t, which become more significant with device scaling, and to the lowest necessary threshold voltage, V_t0, of MOSFETs. As a result of comparing the V_mins of logic, SRAM, and DRAM blocks, it turns out that the SRAM block is problematic because it has the highest V_min despite using RAM repair techniques. Various techniques are thus reviewed, including shortening the data line, up-sizing, and using more relaxed MOSFET scaling. To further reduce the V_mins of the blocks, ΔV_t-immune MOSFETs such as a planar fully-depleted structure (FD-SOI) and fin-type structure (FinFET), and low-V_t0 circuits are discussed, showing the below 0.5-V era feasible to come.