Hardware implementation of pragmatic Trellis Coded Modulation applied to 8PSK and 16QAM for DVB standard

Trellis Coded Modulation (TCM) combines convolutional encoding with PSK or QAM signaling to provide spectrally efficient communication with forward error correction. Although the Ungerboeckpsilas TCM (Trellis Coded Modulation) [1,2] is attractive in terms of high efficiency with low descending data rate by coding and high coding gain, it is difficult to implement. To remove this complexity, a pragmatic approach to the TCM [3], which is realized by employing the de facto convolutional code (constraint length K=7 and rate 1/2), was proposed. This paper presents hardware realization of Pragmatic Trellis Coded Modulation for 8PSK and QAM using two stages approach. In the first stage, the incoming I-channel and Q-channel samples are used to generate soft symbols. A conventional frac12 rate with K=7 Viterbi Decoder then operates on these soft symbols to estimate the coded bits. The uncoded bits are decoded in a second stage, based on the estimated coded bits and the locations of the received symbols. The design has been implemented using high-level Verilog HDL and functionally verified by mapping on to Xilinx Virtex2P FPGA.