Title :
A Clock-Gated Pulse-Triggered D Flip-Flop for Low-Power High-Performance VLSI Synchronous Systems
Author :
Aguirre-Hernandez, M. ; Linares-Aranda, M.
Author_Institution :
Dept. of Electron., INAOE, Puebla
Abstract :
A pulse-triggered D flip-flop with an embedded clock-gating scheme that is suitable for low-power high-speed synchronous applications is presented in this paper. Various flip-flops and different proposed clock-gating circuits were simulated to determine and compare their performance in terms of speed and power dissipation, in order to obtain the best featured one. The circuits were designed using a 0.35 mum CMOS technology and supplied with 3.3 V. As shown in HSPICE simulations, the proposed flip-flop operates up to 1.25 GHz with a delay of 0.3 ns and a power dissipation of 4.1 mW, and it leads to power savings around 45% when used to build a 16-bits binary counter, compared to the counter that uses the non-gated version of the pulse-triggered flip-flop
Keywords :
CMOS integrated circuits; SPICE; VLSI; clocks; counting circuits; flip-flops; low-power electronics; 0.3 ns; 0.35 micron; 16 bit; 3.3 V; 4.1 mW; CMOS technology; HSPICE simulations; binary counter; clock-gated flip-flop; clock-gating circuits; clock-gating scheme; high-performance VLSI synchronous systems; low-power VLSI synchronous systems; low-power high-speed synchronous applications; power dissipation; pulse-triggered D flip-flop; CMOS technology; Circuit simulation; Clocks; Energy consumption; Flip-flops; Inverters; Power dissipation; Proposals; Pulse circuits; Very large scale integration; clock-gating; flip-flop; high-speed; low-power; pulse-triggered; synchronous;
Conference_Titel :
Devices, Circuits and Systems, Proceedings of the 6th International Caribbean Conference on
Conference_Location :
Playa del Carmen
Print_ISBN :
1-4244-0041-4
Electronic_ISBN :
1-4244-0042-2
DOI :
10.1109/ICCDCS.2006.250876
