Title :
Fully parallel fractional motion estimation for H.264/AVC encoder
Author :
Ta, Nam Thang ; Choi, Jun Rim ; Kim, Jae Hoon ; Hwang, Seon Cheol ; Kim, Shi Hye
Author_Institution :
Sch. of Electr. Eng. & Comput. Sci., Kyungpook Nat. Univ., Daegu, South Korea
Abstract :
Fractional motion estimation always takes much processing time because of variety of motion vectors and two-step sequential half-quarter pel. In this paper, we propose the architecture of fractional engine in fully parallel manner. Instead of sequential processing two-step of half-quarter refinement, integer-half-quarter pel is processed in parallel manner in order to double the speed as well as the throughput. Using Chartard 0.18 ¿m CMOS 1P5M technology, the proposed architecture is implemented with 412k logic gates and achieves the throughput of 255 kMBs/s supporting HDTV1080p 30 fps when operating at the frequency of 220 MHz.
Keywords :
CMOS digital integrated circuits; motion estimation; video codecs; CMOS 1P5M technology; H.264/AVC encoder; fractional engine; fully parallel fractional motion estimation; half quarter refinement; size 0.18 mum; Automatic voltage control; CMOS logic circuits; CMOS technology; Computer architecture; Computer science; Engines; HDTV; Hardware; Motion estimation; Throughput; H.264/AVC; fractional; half-quarter pel; integer; motion estimation;
Conference_Titel :
Intelligent Computing and Intelligent Systems, 2009. ICIS 2009. IEEE International Conference on
Conference_Location :
Shanghai
Print_ISBN :
978-1-4244-4754-1
Electronic_ISBN :
978-1-4244-4738-1
DOI :
10.1109/ICICISYS.2009.5357692
