A high-PSRR ADPLL with self-regulated GRO TDC and DCO-dedicated voltage regulator

Author

Yanfeng Li ; Yutao Liu ; Woogeun Rhee ; Zhihua Wang

Author_Institution

Inst. of Microelectron., Tsinghua Univ., Beijing, China

fYear

2015

fDate

27-29 April 2015

Firstpage

1

Lastpage

4

Abstract

This paper describes a PSRR enhancing method for the all-digital phase-locked loop (ADPLL) by utilizing a self-regulated gated ring-oscillator (SR-GRO) time-to-digital converter (TDC) and a voltage regulator just for a digitally-controlled oscillator (DCO). The SR-GRO employs a replica supply noise monitoring circuit which tracks supply noise and enables feed-forward error cancellation over broad spectrum. A prototype ADPLL implemented in 65nm CMOS achieves >25dB PSRR when 100mV_pp 1MHz supply noise is injected to both the TDC and the DCO. Experimental results show that the SR-GRO TDC can also suppress the supply coupling induced phase noise.

Keywords

CMOS integrated circuits; digital phase locked loops; oscillators; time-digital conversion; voltage regulators; CMOS; DCO-dedicated voltage regulator; PSRR enhancing method; SR-GRO; all-digital phase-locked loop; digitally-controlled oscillator; feedforward error cancellation; frequency 1 MHz; high-PSRR ADPLL; replica supply noise monitoring circuit; self-regulated GRO TDC; self-regulated gated ring-oscillator; size 65 nm; supply coupling induced phase noise suppression; time-to-digital converter; voltage 100 mV; Bandwidth; Couplings; Monitoring; Noise; Phase locked loops; Regulators; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, Automation and Test (VLSI-DAT), 2015 International Symposium on

Conference_Location

Hsinchu

Type

conf

DOI

10.1109/VLSI-DAT.2015.7114499

Filename

7114499