Title :
A 2.5 mW/ch, 50 Mcps, 10-analog channel, adaptively biased read-out front-end IC with 9.71 ps-RMS timing resolution for single-photon time-of-flight PET applications in 90 nm CMOS
Author :
Cruz, Hugo ; Hong-Yi Huang ; Shueen-Yu Lee ; Ching-Hsing Luo
Author_Institution :
Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
Abstract :
A 10-channel time-of-flight (TOF) positron emission tomography (PET) IC that uses a digital-to-analog (DAC) - based architecture is implemented in 90nm CMOS process. The DAC is used to compensate for timing resolution variation attributed to amplifier gain fluctuation. Mixed-signal reset signals enhance photon counting speed achieving 5M counts/s/ch. The IC uses adaptive biases to stabilize the gain of preamplifiers and comparators. Multi-stage preamplifiers and comparator architectures were selected for low power. Measurement results show that these techniques enable the IC to achieve 9.71ps-RMS of intrinsic jitter and 181.5ps-FWHM (Full-width-at-half-maximum) timing resolution using an avalanche photo-diode and laser setup while consuming 2.5mW at 0.5V and 1.2V power supplies. The IC was fabricated in a 90nm CMOS process with area of 3.3 × 2.7mm2.
Keywords :
CMOS integrated circuits; biomedical electronics; comparators (circuits); digital-analogue conversion; positron emission tomography; preamplifiers; readout electronics; 10-analog channel adaptively biased read-out front-end IC; CMOS process; DAC; FWHM timing resolution; RMS timing resolution variation; TOF PET IC; adaptive biases; amplifier gain fluctuation; avalanche photodiode; comparator architectures; digital-to-analog based architecture; full-width-at-half-maximum timing resolution; mixed-signal reset signals; multistage preamplifiers; power 25 mW; single-photon time-of-flight PET applications; size 90 nm; time 181.5 ps; time 9.71 ps; time-of-flight positron emission tomography; voltage 0.5 V; voltage 1.2 V; Application specific integrated circuits; Jitter; Photonics; Positron emission tomography; Preamplifiers; Timing;
Conference_Titel :
VLSI Design, Automation and Test (VLSI-DAT), 2015 International Symposium on
Conference_Location :
Hsinchu
DOI :
10.1109/VLSI-DAT.2015.7114501