Title :
A parallel algorithm for standard cell placement
Author :
Horvath, E.I. ; Shankar, R. ; Pandya, A.S.
Author_Institution :
Dept. of Comput. Eng., Florida Atlantic Univ., Boca Raton, FL, USA
Abstract :
Summary form only given. The placement problem is an important issue in the design process of VLSI chips. It is necessary to have an optimum placement so that all electrical connections between cells are routed in a minimum area without violating any physical constraints. The ALOPEX algorithm can easily be implemented in a hierarchical SIMD parallel processing architecture. It requires simple processing elements which do not need to be fully interconnected to implement the algorithm. The ALOPEX algorithm has been shown, through computer simulations, to be applicable to solving the traveling salesman problem. Since the placement problem is similar to the traveling salesman problem, a method of applying the ALOPEX algorithm has been developed for the placement problem, and computer simulations have been performed
Keywords :
VLSI; circuit layout CAD; digital simulation; parallel algorithms; ALOPEX algorithm; VLSI chips; cell placement; computer simulations; electrical connections; hierarchical SIMD parallel processing architecture; parallel algorithm; routing; traveling salesman problem; Backpropagation; Computer architecture; Computer simulation; Concurrent computing; Design engineering; Hip; Parallel algorithms; Parallel processing; Process design; Traveling salesman problems;
Conference_Titel :
Neural Networks, 1991., IJCNN-91-Seattle International Joint Conference on
Conference_Location :
Seattle, WA
Print_ISBN :
0-7803-0164-1
DOI :
10.1109/IJCNN.1991.155476